In a high-frequency transistor, deterioration in gain and a noise characteristic caused by parasitic resistance of the gate are not negligible.
As a method of reducing the gate parasitic resistance, a method of using a finger structure in order to decrease the gate width is known. However, this method has problems that, e.g., the reduction in gate width is limited, and the characteristics deteriorate due to the influence of the wiring parasitic capacitance and substrate parasitic capacitance/resistance because many fingers are necessary.
As a method of solving the above-mentioned problems, there is a method of forming signal terminals at either end of each gate. This method can reduce the gate parasitic resistance to ¼ when compared to a case in which a signal terminal is formed at only one side of each gate (i.e., a case in which a signal is extracted from only one side of each gate).
Unfortunately, this method is disadvantageous in that the wiring structure is complex. In one method, for example, signal lines extracted from gates and signal lines extracted from drains overlap each other, so the gate-to-drain wiring parasitic capacitance (Cgd) increases. When using a transistor as an amplifier, Cgd is multiplied by the gain as a Miller capacitance with respect to the input terminal, so the gain deteriorates. Even when a matching circuit is connected, the gain performance (fmax ((max) or maximum available power gain (MAG)) deteriorates due to the influence of the load resistance. Also, since isolation between the output terminal (drain) and input terminal (gate) deteriorates, the oscillation stability decreases. To increase the stability, the power gain must be decreased, and as a consequence the gain characteristic deteriorates.
Furthermore, a transistor having a round structure in which a Cgd increase is small has been proposed as another method. However, the round structure poses other problems, such as a reduction in degree of freedom of the transistor size and an increase in packaging area.
No conventional technique which suppresses the increase in gate-to-drain capacitance while reducing the gate parasitic resistance is known.